1. Field of Invention
This invention relates to a multi-chips stacked package. More particularly, the present invention is related to a multi-chips stacked package that utilizes one chip electrically connecting to another chip and a substrate through electrically conductive wires directly connecting to said another chip and said substrate respectively to enhance the density of I/O signals and the degree of freedom for laying out the electrical circuits of the package.
2. Related Art
As we know, in the semiconductor industries, the manufacture of semiconductors mainly comprises the manufacture of wafers and the assembly of integrated circuits devices. Therein, the integrated circuits (ICs) devices are completely formed by the processes of forming integrated circuits devices on the semiconductor wafers, sawing the wafers into individual integrated circuits devices, placing the individual integrated circuits devices on the substrates, electrically connecting the integrated circuits devices to the substrates and encapsulating the integrated circuits devices and substrates to form a plurality of assembly packages. Due to the encapsulation covering the integrated circuits devices, the integrated circuits devices are able to be protected from the damp entering. In addition, the assembly packages may further provide external terminals for connecting to printed circuit board (PCB).
However, recently, integrated circuits packaging technology is becoming a limiting factor for the development in packaging integrated circuits devices of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
Due to the assembly package in miniature and the integrated circuits operation in high frequency, MCM (multi-chips module) packages are commonly used in said assembly packages and electronic devices. Usually, said MCM package mainly comprises at least two chips encapsulated therein in a parallel manner to form a side-by-side package, for example a processor unit, a memory unit and related logic units, so as to upgrade the electrical performance of said assembly package. In addition, the electrical paths between the chips in said MCM package are short so as to reduce the signal delay and save the reading and writing time.
Per the above-mentioned, a multi-chips stacked package is provided, as shown in FIG. 1, as a standard and common design. Referring to FIG. 1, it is characterized that an upper chip 110 is flipped over and disposed above an opening 122 passing through the upper surface 124 and the lower surface 126 of the substrate 120, and electrically connected to the substrate 120 through electrically conductive bumps 150; and a lower chip 130 is accommodated in the opening 122 and electrically connected to the upper chip 110 through electrically conductive bumps 160. Generally speaking, the upper chip 110 and the lower chip 130 are a memory chip and a logic chip respectively. In such a manner, the electrical signals are able to be integrated in the package and then are transmitted to external devices through solder balls 128 attached to the lower surface 126 of the substrate 120. Thus, the size of said multi-chips stacked package is reduced and the transmission path of the electrical signals are shortened. Namely, the signal delay is reduced and the electrical performance of said multi-chips stacked package is upgraded.
As mentioned above and per the conventional invention as shown in FIG. 1, the upper chip 110 is electrically connected to the substrate 120 through electrically conductive bumps 150. However, before the upper chip 110 is bonded to the lower chip 130, there are flip-chip pads and under bump metallization layers formed on the upper chip 110 and the lower chip 130. Accordingly, the manufacturing cost is increased and the process is caused to be more complex. Besides, the electrical signals of the lower chip 130 are transmitted to the substrate 120 through the electrically conductive bumps 150 and 160, and the upper chip 110. Thus, the design of the electrical circuits of the upper chip 110 are usually made in accordance with the lower chip 130 and are taken into more consideration according to the integration of the upper chip 110 and the lower chip 130. Consequently, it lowers the degree of freedom of designing the upper chip 110 and laying out the circuits of the upper chip 110.
Therefore, providing another multi-chips stacked package to solve the mentioned-above disadvantages is the most important task in this invention.